An inspection apparatus for a circuit pattern of a semiconductor device or liquid crystals has the function to compare an image obtained under irradiation of light or an electron beam with a reference image represented by a standard image or an adjoining image, extract a pixel affected by a difference to judge it as a defect and output a coordinate thereof.
In a circuit pattern as a target of the inspection apparatus, the pattern density per unit area has been quadrupping every 3 years. This is realized by the pattern shrinkage. The shrinkage causes the difference between a defect and a normal portion becomes very small. Then, by setting a threshold value between a signal value of the defect and that of the normal portion and discriminating the defect from the normal portion, a minute defect can be detected. Especially, in a memory mat of a memory device, one memory cell is one bit of memory, but even if a defect is present in a single memory cell, the total device can operate normally by virtue of a redundancy circuit technique and therefore, the miniaturization is further spurred. On the other hand, in a peripheral circuit other than the memory mat, even a single defect causes the device defective and so the pattern dimension is not so miniaturized as in the case of the memory mat. When reviewing a distribution of locations where pattern defects occurs, it is indicated that the density of defects is high in the memory mat. Especially, at the outer-most of the memory mat, the pattern density changes abruptly and hence, production in photolithography process is very difficult and the defect density is very high.
A technique for inspecting such a periodical pattern portion as in the memory mat and a region having no repetiveness discriminatively from each other has been known (see Patent Literature 1). But a technique capable of detecting defects in both of them at a same time with high accuracies has not yet been known.
In inspecting a semiconductor wafer in which semiconductor devices are formed, there are die to die comparison method and a cell comparison method which inspect only cell region having pattern repetiveness in a die. The cell comparison method uses the repetiveness and cannot be applied to a peripheral circuit without repetiveness.
Citation List
Patent Literature
    Patent Literature 1: JP-A-3-232250